Syntax of GFX950 Instructions — LLVM 23.1.0 documentation

# Syntax of GFX950 Instructions

## Introduction

This document describes the syntax of GFX950 instructions.

## Notation

Notation used in this document is explained here.

## Overview

An overview of generic syntax and other features of AMDGPU instructions may be found in this document.

## Instructions

### DS

    INSTRUCTION                    DST       SRC0      SRC1      SRC2           MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————
    ds_add_f32                               addr,     data0                    offset gds
    ds_add_f64                               addr,     data0                    offset gds
    ds_add_rtn_f32                 vdst,     addr,     data0                    offset gds
    ds_add_rtn_f64                 vdst,     addr,     data0                    offset gds
    ds_add_rtn_u32                 vdst,     addr,     data0                    offset gds
    ds_add_rtn_u64                 vdst,     addr,     data0                    offset gds
    ds_add_u32                               addr,     data0                    offset gds
    ds_add_u64                               addr,     data0                    offset gds
    ds_and_b32                               addr,     data0                    offset gds
    ds_and_b64                               addr,     data0                    offset gds
    ds_and_rtn_b32                 vdst,     addr,     data0                    offset gds
    ds_and_rtn_b64                 vdst,     addr,     data0                    offset gds
    ds_append                      vdst                                         offset gds
    ds_bpermute_b32                vdst,     addr,     data0                    offset gds
    ds_cmpst_b32                             addr,     data0,    data1          offset gds
    ds_cmpst_b64                             addr,     data0,    data1          offset gds
    ds_cmpst_f32                             addr,     data0,    data1          offset gds
    ds_cmpst_f64                             addr,     data0,    data1          offset gds
    ds_cmpst_rtn_b32               vdst,     addr,     data0,    data1          offset gds
    ds_cmpst_rtn_b64               vdst,     addr,     data0,    data1          offset gds
    ds_cmpst_rtn_f32               vdst,     addr,     data0,    data1          offset gds
    ds_cmpst_rtn_f64               vdst,     addr,     data0,    data1          offset gds
    ds_condxchg32_rtn_b64          vdst,     addr,     data0                    offset gds
    ds_consume                     vdst                                         offset gds
    ds_dec_rtn_u32                 vdst,     addr,     data0                    offset gds
    ds_dec_rtn_u64                 vdst,     addr,     data0                    offset gds
    ds_dec_u32                               addr,     data0                    offset gds
    ds_dec_u64                               addr,     data0                    offset gds
    ds_inc_rtn_u32                 vdst,     addr,     data0                    offset gds
    ds_inc_rtn_u64                 vdst,     addr,     data0                    offset gds
    ds_inc_u32                               addr,     data0                    offset gds
    ds_inc_u64                               addr,     data0                    offset gds
    ds_max_f32                               addr,     data0                    offset gds
    ds_max_f64                               addr,     data0                    offset gds
    ds_max_i32                               addr,     data0                    offset gds
    ds_max_i64                               addr,     data0                    offset gds
    ds_max_rtn_f32                 vdst,     addr,     data0                    offset gds
    ds_max_rtn_f64                 vdst,     addr,     data0                    offset gds
    ds_max_rtn_i32                 vdst,     addr,     data0                    offset gds
    ds_max_rtn_i64                 vdst,     addr,     data0                    offset gds
    ds_max_rtn_u32                 vdst,     addr,     data0                    offset gds
    ds_max_rtn_u64                 vdst,     addr,     data0                    offset gds
    ds_max_u32                               addr,     data0                    offset gds
    ds_max_u64                               addr,     data0                    offset gds
    ds_min_f32                               addr,     data0                    offset gds
    ds_min_f64                               addr,     data0                    offset gds
    ds_min_i32                               addr,     data0                    offset gds
    ds_min_i64                               addr,     data0                    offset gds
    ds_min_rtn_f32                 vdst,     addr,     data0                    offset gds
    ds_min_rtn_f64                 vdst,     addr,     data0                    offset gds
    ds_min_rtn_i32                 vdst,     addr,     data0                    offset gds
    ds_min_rtn_i64                 vdst,     addr,     data0                    offset gds
    ds_min_rtn_u32                 vdst,     addr,     data0                    offset gds
    ds_min_rtn_u64                 vdst,     addr,     data0                    offset gds
    ds_min_u32                               addr,     data0                    offset gds
    ds_min_u64                               addr,     data0                    offset gds
    ds_mskor_b32                             addr,     data0,    data1          offset gds
    ds_mskor_b64                             addr,     data0,    data1          offset gds
    ds_mskor_rtn_b32               vdst,     addr,     data0,    data1          offset gds
    ds_mskor_rtn_b64               vdst,     addr,     data0,    data1          offset gds
    ds_nop                                                                      offset gds
    ds_or_b32                                addr,     data0                    offset gds
    ds_or_b64                                addr,     data0                    offset gds
    ds_or_rtn_b32                  vdst,     addr,     data0                    offset gds
    ds_or_rtn_b64                  vdst,     addr,     data0                    offset gds
    ds_permute_b32                 vdst,     addr,     data0                    offset gds
    ds_pk_add_bf16                           addr,     data0                    offset gds
    ds_pk_add_f16                            addr,     data0                    offset gds
    ds_pk_add_rtn_bf16             vdst,     addr,     data0                    offset gds
    ds_pk_add_rtn_f16              vdst,     addr,     data0                    offset gds
    ds_read2_b32                   vdst,     addr                               offset0 offset1 gds
    ds_read2_b64                   vdst,     addr                               offset0 offset1 gds
    ds_read2st64_b32               vdst,     addr                               offset0 offset1 gds
    ds_read2st64_b64               vdst,     addr                               offset0 offset1 gds
    ds_read_addtid_b32             vdst                                         offset gds
    ds_read_b128                   vdst,     addr                               offset gds
    ds_read_b32                    vdst,     addr                               offset gds
    ds_read_b64                    vdst,     addr                               offset gds
    ds_read_b64_tr_b16             vdst,     addr                               offset gds
    ds_read_b64_tr_b4              vdst,     addr                               offset gds
    ds_read_b64_tr_b8              vdst,     addr                               offset gds
    ds_read_b96                    vdst,     addr                               offset gds
    ds_read_b96_tr_b6              vdst,     addr                               offset gds
    ds_read_i16                    vdst,     addr                               offset gds
    ds_read_i8                     vdst,     addr                               offset gds
    ds_read_i8_d16                 vdst,     addr                               offset gds
    ds_read_i8_d16_hi              vdst,     addr                               offset gds
    ds_read_u16                    vdst,     addr                               offset gds
    ds_read_u16_d16                vdst,     addr                               offset gds
    ds_read_u16_d16_hi             vdst,     addr                               offset gds
    ds_read_u8                     vdst,     addr                               offset gds
    ds_read_u8_d16                 vdst,     addr                               offset gds
    ds_read_u8_d16_hi              vdst,     addr                               offset gds
    ds_rsub_rtn_u32                vdst,     addr,     data0                    offset gds
    ds_rsub_rtn_u64                vdst,     addr,     data0                    offset gds
    ds_rsub_u32                              addr,     data0                    offset gds
    ds_rsub_u64                              addr,     data0                    offset gds
    ds_sub_rtn_u32                 vdst,     addr,     data0                    offset gds
    ds_sub_rtn_u64                 vdst,     addr,     data0                    offset gds
    ds_sub_u32                               addr,     data0                    offset gds
    ds_sub_u64                               addr,     data0                    offset gds
    ds_swizzle_b32                 vdst,     addr                               offset gds
    ds_wrap_rtn_b32                vdst,     addr,     data0,    data1          offset gds
    ds_write2_b32                            addr,     data0,    data1          offset0 offset1 gds
    ds_write2_b64                            addr,     data0,    data1          offset0 offset1 gds
    ds_write2st64_b32                        addr,     data0,    data1          offset0 offset1 gds
    ds_write2st64_b64                        addr,     data0,    data1          offset0 offset1 gds
    ds_write_addtid_b32                      data0                              offset gds
    ds_write_b128                            addr,     data0                    offset gds
    ds_write_b16                             addr,     data0                    offset gds
    ds_write_b16_d16_hi                      addr,     data0                    offset gds
    ds_write_b32                             addr,     data0                    offset gds
    ds_write_b64                             addr,     data0                    offset gds
    ds_write_b8                              addr,     data0                    offset gds
    ds_write_b8_d16_hi                       addr,     data0                    offset gds
    ds_write_b96                             addr,     data0                    offset gds
    ds_wrxchg2_rtn_b32             vdst,     addr,     data0,    data1          offset0 offset1 gds
    ds_wrxchg2_rtn_b64             vdst,     addr,     data0,    data1          offset0 offset1 gds
    ds_wrxchg2st64_rtn_b32         vdst,     addr,     data0,    data1          offset0 offset1 gds
    ds_wrxchg2st64_rtn_b64         vdst,     addr,     data0,    data1          offset0 offset1 gds
    ds_wrxchg_rtn_b32              vdst,     addr,     data0                    offset gds
    ds_wrxchg_rtn_b64              vdst,     addr,     data0                    offset gds
    ds_xor_b32                               addr,     data0                    offset gds
    ds_xor_b64                               addr,     data0                    offset gds
    ds_xor_rtn_b32                 vdst,     addr,     data0                    offset gds
    ds_xor_rtn_b64                 vdst,     addr,     data0                    offset gds

### FLAT

    INSTRUCTION                    DST       SRC0      SRC1           MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————
    flat_atomic_add                vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_add_f32            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_add_f64            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_add_x2             vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_and                vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_and_x2             vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_cmpswap            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_cmpswap_x2         vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_dec                vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_dec_x2             vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_inc                vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_inc_x2             vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_max_f64            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_min_f64            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_or                 vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_or_x2              vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_pk_add_bf16        vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_pk_add_f16         vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_smax               vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_smax_x2            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_smin               vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_smin_x2            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_sub                vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_sub_x2             vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_swap               vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_swap_x2            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_umax               vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_umax_x2            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_umin               vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_umin_x2            vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_xor                vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_atomic_xor_x2             vdst,     addr,     data           offset12 sc0 sc1 nt
    flat_load_dword                vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_dwordx2              vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_dwordx3              vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_dwordx4              vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_sbyte                vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_sbyte_d16            vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_sbyte_d16_hi         vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_short_d16            vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_short_d16_hi         vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_sshort               vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_ubyte                vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_ubyte_d16            vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_ubyte_d16_hi         vdst,     addr                     offset12 sc0 sc1 nt
    flat_load_ushort               vdst,     addr                     offset12 sc0 sc1 nt
    flat_store_byte                          addr,     data           offset12 sc0 sc1 nt
    flat_store_byte_d16_hi                   addr,     data           offset12 sc0 sc1 nt
    flat_store_dword                         addr,     data           offset12 sc0 sc1 nt
    flat_store_dwordx2                       addr,     data           offset12 sc0 sc1 nt
    flat_store_dwordx3                       addr,     data           offset12 sc0 sc1 nt
    flat_store_dwordx4                       addr,     data           offset12 sc0 sc1 nt
    flat_store_short                         addr,     data           offset12 sc0 sc1 nt
    flat_store_short_d16_hi                  addr,     data           offset12 sc0 sc1 nt

### FLAT_GLBL

    INSTRUCTION                    DST       SRC0      SRC1      SRC2           MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————
    global_atomic_add              vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_add_f32          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_add_f64          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_add_x2           vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_and              vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_and_x2           vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_cmpswap          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_cmpswap_x2       vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_dec              vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_dec_x2           vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_inc              vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_inc_x2           vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_max_f64          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_min_f64          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_or               vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_or_x2            vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_pk_add_bf16      vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_pk_add_f16       vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_smax             vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_smax_x2          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_smin             vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_smin_x2          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_sub              vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_sub_x2           vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_swap             vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_swap_x2          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_umax             vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_umax_x2          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_umin             vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_umin_x2          vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_xor              vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_atomic_xor_x2           vdst,     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_load_dword              vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_dwordx2            vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_dwordx3            vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_dwordx4            vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_dword          vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_dwordx3        vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_dwordx4        vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_sbyte          vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_sshort         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_ubyte          vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_lds_ushort         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_sbyte              vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_sbyte_d16          vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_sbyte_d16_hi       vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_short_d16          vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_short_d16_hi       vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_sshort             vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_ubyte              vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_ubyte_d16          vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_ubyte_d16_hi       vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_load_ushort             vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    global_store_byte                        addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_byte_d16_hi                 addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_dword                       addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_dwordx2                     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_dwordx3                     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_dwordx4                     addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_short                       addr,     data,     saddr          offset12 sc0 sc1 nt
    global_store_short_d16_hi                addr,     data,     saddr          offset12 sc0 sc1 nt

### FLAT_SCRATCH

    INSTRUCTION                    DST       SRC0      SRC1      SRC2           MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————
    scratch_load_dword             vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_dwordx2           vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_dwordx3           vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_dwordx4           vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_lds_dword         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_lds_sbyte         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_lds_sshort        vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_lds_ubyte         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_lds_ushort        vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_sbyte             vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_sbyte_d16         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_sbyte_d16_hi      vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_short_d16         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_short_d16_hi      vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_sshort            vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_ubyte             vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_ubyte_d16         vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_ubyte_d16_hi      vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_load_ushort            vdst,     addr,     saddr                    offset12 sc0 sc1 nt
    scratch_store_byte                       addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_byte_d16_hi                addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_dword                      addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_dwordx2                    addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_dwordx3                    addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_dwordx4                    addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_short                      addr,     data,     saddr          offset12 sc0 sc1 nt
    scratch_store_short_d16_hi               addr,     data,     saddr          offset12 sc0 sc1 nt

### MTBUF

    INSTRUCTION                     DST    SRC0   SRC1   SRC2      MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————————————————————
    tbuffer_load_format_d16_x       vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_d16_xy      vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_d16_xyz     vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_d16_xyzw    vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_x           vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_xy          vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_xyz         vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_load_format_xyzw        vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_d16_x      vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_d16_xy     vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_d16_xyz    vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_d16_xyzw   vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_x          vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_xy         vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_xyz        vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt
    tbuffer_store_format_xyzw       vdata, vaddr, srsrc, soffset   offset12 offen idxen format sc0 sc1 nt

### MUBUF

    INSTRUCTION                    DST      SRC0     SRC1     SRC2      MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————————
    buffer_atomic_add              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_add_f32          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_add_f64          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_add_x2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_and              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_and_x2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_cmpswap          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_cmpswap_x2       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_dec              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_dec_x2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_inc              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_inc_x2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_max_f64          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_min_f64          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_or               vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_or_x2            vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_pk_add_bf16      vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_pk_add_f16       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_smax             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_smax_x2          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_smin             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_smin_x2          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_sub              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_sub_x2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_swap             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_swap_x2          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_umax             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_umax_x2          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_umin             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_umin_x2          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_xor              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_atomic_xor_x2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_inv                                                          offset12 offen idxen lds sc0 sc1 nt
    buffer_load_dword              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_dwordx2            vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_dwordx3            vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_dwordx4            vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_d16_hi_x    vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_d16_x       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_d16_xy      vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_d16_xyz     vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_d16_xyzw    vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_x           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_xy          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_xyz         vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_format_xyzw        vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_sbyte              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_sbyte_d16          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_sbyte_d16_hi       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_short_d16          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_short_d16_hi       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_sshort             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_ubyte              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_ubyte_d16          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_ubyte_d16_hi       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_load_ushort             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_byte              vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_byte_d16_hi       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_dword             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_dwordx2           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_dwordx3           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_dwordx4           vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_d16_hi_x   vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_d16_x      vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_d16_xy     vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_d16_xyz    vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_d16_xyzw   vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_x          vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_xy         vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_xyz        vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_format_xyzw       vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_short             vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_store_short_d16_hi      vdata,   vaddr,   srsrc,   soffset   offset12 offen idxen lds sc0 sc1 nt
    buffer_wbl2                                                         offset12 offen idxen lds sc0 sc1 nt

### SMEM

    INSTRUCTION                    DST       SRC0      SRC1
    —————————————————————————————————————————————————————————————
    s_atc_probe                    sdata,    sbase,    soffset
    s_atc_probe_buffer             sdata,    sbase,    soffset
    s_atomic_add                   sdata,    sbase,    soffset
    s_atomic_add_x2                sdata,    sbase,    soffset
    s_atomic_and                   sdata,    sbase,    soffset
    s_atomic_and_x2                sdata,    sbase,    soffset
    s_atomic_cmpswap               sdata,    sbase,    soffset
    s_atomic_cmpswap_x2            sdata,    sbase,    soffset
    s_atomic_dec                   sdata,    sbase,    soffset
    s_atomic_dec_x2                sdata,    sbase,    soffset
    s_atomic_inc                   sdata,    sbase,    soffset
    s_atomic_inc_x2                sdata,    sbase,    soffset
    s_atomic_or                    sdata,    sbase,    soffset
    s_atomic_or_x2                 sdata,    sbase,    soffset
    s_atomic_smax                  sdata,    sbase,    soffset
    s_atomic_smax_x2               sdata,    sbase,    soffset
    s_atomic_smin                  sdata,    sbase,    soffset
    s_atomic_smin_x2               sdata,    sbase,    soffset
    s_atomic_sub                   sdata,    sbase,    soffset
    s_atomic_sub_x2                sdata,    sbase,    soffset
    s_atomic_swap                  sdata,    sbase,    soffset
    s_atomic_swap_x2               sdata,    sbase,    soffset
    s_atomic_umax                  sdata,    sbase,    soffset
    s_atomic_umax_x2               sdata,    sbase,    soffset
    s_atomic_umin                  sdata,    sbase,    soffset
    s_atomic_umin_x2               sdata,    sbase,    soffset
    s_atomic_xor                   sdata,    sbase,    soffset
    s_atomic_xor_x2                sdata,    sbase,    soffset
    s_buffer_atomic_add            sdata,    sbase,    soffset
    s_buffer_atomic_add_x2         sdata,    sbase,    soffset
    s_buffer_atomic_and            sdata,    sbase,    soffset
    s_buffer_atomic_and_x2         sdata,    sbase,    soffset
    s_buffer_atomic_cmpswap        sdata,    sbase,    soffset
    s_buffer_atomic_cmpswap_x2     sdata,    sbase,    soffset
    s_buffer_atomic_dec            sdata,    sbase,    soffset
    s_buffer_atomic_dec_x2         sdata,    sbase,    soffset
    s_buffer_atomic_inc            sdata,    sbase,    soffset
    s_buffer_atomic_inc_x2         sdata,    sbase,    soffset
    s_buffer_atomic_or             sdata,    sbase,    soffset
    s_buffer_atomic_or_x2          sdata,    sbase,    soffset
    s_buffer_atomic_smax           sdata,    sbase,    soffset
    s_buffer_atomic_smax_x2        sdata,    sbase,    soffset
    s_buffer_atomic_smin           sdata,    sbase,    soffset
    s_buffer_atomic_smin_x2        sdata,    sbase,    soffset
    s_buffer_atomic_sub            sdata,    sbase,    soffset
    s_buffer_atomic_sub_x2         sdata,    sbase,    soffset
    s_buffer_atomic_swap           sdata,    sbase,    soffset
    s_buffer_atomic_swap_x2        sdata,    sbase,    soffset
    s_buffer_atomic_umax           sdata,    sbase,    soffset
    s_buffer_atomic_umax_x2        sdata,    sbase,    soffset
    s_buffer_atomic_umin           sdata,    sbase,    soffset
    s_buffer_atomic_umin_x2        sdata,    sbase,    soffset
    s_buffer_atomic_xor            sdata,    sbase,    soffset
    s_buffer_atomic_xor_x2         sdata,    sbase,    soffset
    s_buffer_load_dword            sdata,    sbase,    soffset
    s_buffer_load_dwordx16         sdata,    sbase,    soffset
    s_buffer_load_dwordx2          sdata,    sbase,    soffset
    s_buffer_load_dwordx4          sdata,    sbase,    soffset
    s_buffer_load_dwordx8          sdata,    sbase,    soffset
    s_buffer_store_dword           sdata,    sbase,    soffset
    s_buffer_store_dwordx2         sdata,    sbase,    soffset
    s_buffer_store_dwordx4         sdata,    sbase,    soffset
    s_dcache_discard                         sbase,    soffset
    s_dcache_discard_x2                      sbase,    soffset
    s_dcache_inv
    s_dcache_inv_vol
    s_dcache_wb
    s_dcache_wb_vol
    s_load_dword                   sdata,    sbase,    soffset
    s_load_dwordx16                sdata,    sbase,    soffset
    s_load_dwordx2                 sdata,    sbase,    soffset
    s_load_dwordx4                 sdata,    sbase,    soffset
    s_load_dwordx8                 sdata,    sbase,    soffset
    s_memrealtime                  sdata
    s_memtime                      sdata
    s_scratch_load_dword           sdata,    sbase,    soffset
    s_scratch_load_dwordx2         sdata,    sbase,    soffset
    s_scratch_load_dwordx4         sdata,    sbase,    soffset
    s_scratch_store_dword          sdata,    sbase,    soffset
    s_scratch_store_dwordx2        sdata,    sbase,    soffset
    s_scratch_store_dwordx4        sdata,    sbase,    soffset
    s_store_dword                  sdata,    sbase,    soffset
    s_store_dwordx2                sdata,    sbase,    soffset
    s_store_dwordx4                sdata,    sbase,    soffset

### SOP1

    INSTRUCTION                    DST       SRC
    ———————————————————————————————————————————————————
    s_abs_i32                      sdst,     ssrc0
    s_and_saveexec_b64             sdst,     ssrc0
    s_andn1_saveexec_b64           sdst,     ssrc0
    s_andn1_wrexec_b64             sdst,     ssrc0
    s_andn2_saveexec_b64           sdst,     ssrc0
    s_andn2_wrexec_b64             sdst,     ssrc0
    s_bcnt0_i32_b32                sdst,     ssrc0
    s_bcnt0_i32_b64                sdst,     ssrc0
    s_bcnt1_i32_b32                sdst,     ssrc0
    s_bcnt1_i32_b64                sdst,     ssrc0
    s_bitreplicate_b64_b32         sdst,     ssrc0
    s_bitset0_b32                  sdst,     ssrc0
    s_bitset0_b64                  sdst,     ssrc0
    s_bitset1_b32                  sdst,     ssrc0
    s_bitset1_b64                  sdst,     ssrc0
    s_brev_b32                     sdst,     ssrc0
    s_brev_b64                     sdst,     ssrc0
    s_cbranch_join                           ssrc0
    s_cmov_b32                     sdst,     ssrc0
    s_cmov_b64                     sdst,     ssrc0
    s_ff0_i32_b32                  sdst,     ssrc0
    s_ff0_i32_b64                  sdst,     ssrc0
    s_ff1_i32_b32                  sdst,     ssrc0
    s_ff1_i32_b64                  sdst,     ssrc0
    s_flbit_i32                    sdst,     ssrc0
    s_flbit_i32_b32                sdst,     ssrc0
    s_flbit_i32_b64                sdst,     ssrc0
    s_flbit_i32_i64                sdst,     ssrc0
    s_getpc_b64                    sdst
    s_mov_b32                      sdst,     ssrc0
    s_mov_b64                      sdst,     ssrc0
    s_movreld_b32                  sdst,     ssrc0
    s_movreld_b64                  sdst,     ssrc0
    s_movrels_b32                  sdst,     ssrc0
    s_movrels_b64                  sdst,     ssrc0
    s_nand_saveexec_b64            sdst,     ssrc0
    s_nor_saveexec_b64             sdst,     ssrc0
    s_not_b32                      sdst,     ssrc0
    s_not_b64                      sdst,     ssrc0
    s_or_saveexec_b64              sdst,     ssrc0
    s_orn1_saveexec_b64            sdst,     ssrc0
    s_orn2_saveexec_b64            sdst,     ssrc0
    s_quadmask_b32                 sdst,     ssrc0
    s_quadmask_b64                 sdst,     ssrc0
    s_rfe_b64                                ssrc0
    s_set_gpr_idx_idx                        ssrc0
    s_setpc_b64                              ssrc0
    s_sext_i32_i16                 sdst,     ssrc0
    s_sext_i32_i8                  sdst,     ssrc0
    s_swappc_b64                   sdst,     ssrc0
    s_wqm_b32                      sdst,     ssrc0
    s_wqm_b64                      sdst,     ssrc0
    s_xnor_saveexec_b64            sdst,     ssrc0
    s_xor_saveexec_b64             sdst,     ssrc0

### SOP2

    INSTRUCTION                    DST       SRC0      SRC1
    —————————————————————————————————————————————————————————————
    s_absdiff_i32                  sdst,     ssrc0,    ssrc1
    s_add_i32                      sdst,     ssrc0,    ssrc1
    s_add_u32                      sdst,     ssrc0,    ssrc1
    s_addc_u32                     sdst,     ssrc0,    ssrc1
    s_and_b32                      sdst,     ssrc0,    ssrc1
    s_and_b64                      sdst,     ssrc0,    ssrc1
    s_andn2_b32                    sdst,     ssrc0,    ssrc1
    s_andn2_b64                    sdst,     ssrc0,    ssrc1
    s_ashr_i32                     sdst,     ssrc0,    ssrc1
    s_ashr_i64                     sdst,     ssrc0,    ssrc1
    s_bfe_i32                      sdst,     ssrc0,    ssrc1
    s_bfe_i64                      sdst,     ssrc0,    ssrc1
    s_bfe_u32                      sdst,     ssrc0,    ssrc1
    s_bfe_u64                      sdst,     ssrc0,    ssrc1
    s_bfm_b32                      sdst,     ssrc0,    ssrc1
    s_bfm_b64                      sdst,     ssrc0,    ssrc1
    s_cbranch_g_fork                         ssrc0,    ssrc1
    s_cselect_b32                  sdst,     ssrc0,    ssrc1
    s_cselect_b64                  sdst,     ssrc0,    ssrc1
    s_lshl1_add_u32                sdst,     ssrc0,    ssrc1
    s_lshl2_add_u32                sdst,     ssrc0,    ssrc1
    s_lshl3_add_u32                sdst,     ssrc0,    ssrc1
    s_lshl4_add_u32                sdst,     ssrc0,    ssrc1
    s_lshl_b32                     sdst,     ssrc0,    ssrc1
    s_lshl_b64                     sdst,     ssrc0,    ssrc1
    s_lshr_b32                     sdst,     ssrc0,    ssrc1
    s_lshr_b64                     sdst,     ssrc0,    ssrc1
    s_max_i32                      sdst,     ssrc0,    ssrc1
    s_max_u32                      sdst,     ssrc0,    ssrc1
    s_min_i32                      sdst,     ssrc0,    ssrc1
    s_min_u32                      sdst,     ssrc0,    ssrc1
    s_mul_hi_i32                   sdst,     ssrc0,    ssrc1
    s_mul_hi_u32                   sdst,     ssrc0,    ssrc1
    s_mul_i32                      sdst,     ssrc0,    ssrc1
    s_nand_b32                     sdst,     ssrc0,    ssrc1
    s_nand_b64                     sdst,     ssrc0,    ssrc1
    s_nor_b32                      sdst,     ssrc0,    ssrc1
    s_nor_b64                      sdst,     ssrc0,    ssrc1
    s_or_b32                       sdst,     ssrc0,    ssrc1
    s_or_b64                       sdst,     ssrc0,    ssrc1
    s_orn2_b32                     sdst,     ssrc0,    ssrc1
    s_orn2_b64                     sdst,     ssrc0,    ssrc1
    s_pack_hh_b32_b16              sdst,     ssrc0,    ssrc1
    s_pack_lh_b32_b16              sdst,     ssrc0,    ssrc1
    s_pack_ll_b32_b16              sdst,     ssrc0,    ssrc1
    s_rfe_restore_b64                        ssrc0,    ssrc1
    s_sub_i32                      sdst,     ssrc0,    ssrc1
    s_sub_u32                      sdst,     ssrc0,    ssrc1
    s_subb_u32                     sdst,     ssrc0,    ssrc1
    s_xnor_b32                     sdst,     ssrc0,    ssrc1
    s_xnor_b64                     sdst,     ssrc0,    ssrc1
    s_xor_b32                      sdst,     ssrc0,    ssrc1
    s_xor_b64                      sdst,     ssrc0,    ssrc1

### SOPC

    INSTRUCTION                    SRC0      SRC1
    ———————————————————————————————————————————————————
    s_bitcmp0_b32                  ssrc0,    ssrc1
    s_bitcmp0_b64                  ssrc0,    ssrc1
    s_bitcmp1_b32                  ssrc0,    ssrc1
    s_bitcmp1_b64                  ssrc0,    ssrc1
    s_cmp_eq_i32                   ssrc0,    ssrc1
    s_cmp_eq_u32                   ssrc0,    ssrc1
    s_cmp_eq_u64                   ssrc0,    ssrc1
    s_cmp_ge_i32                   ssrc0,    ssrc1
    s_cmp_ge_u32                   ssrc0,    ssrc1
    s_cmp_gt_i32                   ssrc0,    ssrc1
    s_cmp_gt_u32                   ssrc0,    ssrc1
    s_cmp_le_i32                   ssrc0,    ssrc1
    s_cmp_le_u32                   ssrc0,    ssrc1
    s_cmp_lg_i32                   ssrc0,    ssrc1
    s_cmp_lg_u32                   ssrc0,    ssrc1
    s_cmp_lg_u64                   ssrc0,    ssrc1
    s_cmp_lt_i32                   ssrc0,    ssrc1
    s_cmp_lt_u32                   ssrc0,    ssrc1
    s_set_gpr_idx_on               ssrc0,    ssrc1
    s_setvskip                     ssrc0,    ssrc1

### SOPK

    INSTRUCTION                    DST       SRC
    ———————————————————————————————————————————————————
    s_addk_i32                     sdst,     simm16
    s_call_b64                     sdst,     simm16
    s_cbranch_i_fork               sdst,     simm16
    s_cmovk_i32                    sdst,     simm16
    s_cmpk_eq_i32                  sdst,     simm16
    s_cmpk_eq_u32                  sdst,     simm16
    s_cmpk_ge_i32                  sdst,     simm16
    s_cmpk_ge_u32                  sdst,     simm16
    s_cmpk_gt_i32                  sdst,     simm16
    s_cmpk_gt_u32                  sdst,     simm16
    s_cmpk_le_i32                  sdst,     simm16
    s_cmpk_le_u32                  sdst,     simm16
    s_cmpk_lg_i32                  sdst,     simm16
    s_cmpk_lg_u32                  sdst,     simm16
    s_cmpk_lt_i32                  sdst,     simm16
    s_cmpk_lt_u32                  sdst,     simm16
    s_getreg_b32                   sdst,     simm16
    s_movk_i32                     sdst,     simm16
    s_mulk_i32                     sdst,     simm16
    s_setreg_b32                   simm16,   sdst
    s_setreg_imm32_b32             simm16,   literal

### SOPP

    INSTRUCTION                    SRC
    —————————————————————————————————————————
    s_barrier
    s_branch                       simm16
    s_cbranch_cdbgsys              simm16
    s_cbranch_cdbgsys_and_user     simm16
    s_cbranch_cdbgsys_or_user      simm16
    s_cbranch_cdbguser             simm16
    s_cbranch_execnz               simm16
    s_cbranch_execz                simm16
    s_cbranch_scc0                 simm16
    s_cbranch_scc1                 simm16
    s_cbranch_vccnz                simm16
    s_cbranch_vccz                 simm16
    s_decperflevel                 simm16
    s_endpgm
    s_endpgm_ordered_ps_done
    s_endpgm_saved
    s_icache_inv
    s_incperflevel                 simm16
    s_nop                          simm16
    s_sendmsg                      simm16
    s_sendmsghalt                  simm16
    s_set_gpr_idx_mode             simm16
    s_set_gpr_idx_off
    s_set_valu_coexec_mode         simm16
    s_sethalt                      simm16
    s_setkill                      simm16
    s_setprio                      simm16
    s_sleep                        simm16
    s_trap                         simm16
    s_ttracedata
    s_waitcnt                      simm16
    s_wakeup

### VOP1

    INSTRUCTION                      DST   SRC    MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_accvgpr_mov_b32                vdst, src0
    v_accvgpr_mov_b32_dpp            vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_accvgpr_mov_b32_sdwa           vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_bfrev_b32                      vdst, src0
    v_bfrev_b32_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_bfrev_b32_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_ceil_f16                       vdst, src0
    v_ceil_f16_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ceil_f16_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_ceil_f32                       vdst, src0
    v_ceil_f32_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ceil_f32_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_ceil_f64                       vdst, src0
    v_ceil_f64_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_clrexcp
    v_cos_f16                        vdst, src0
    v_cos_f16_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cos_f16_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cos_f32                        vdst, src0
    v_cos_f32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cos_f32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f16_f32                    vdst, src0
    v_cvt_f16_f32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f16_f32_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f16_i16                    vdst, src0
    v_cvt_f16_i16_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f16_i16_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f16_u16                    vdst, src0
    v_cvt_f16_u16_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f16_u16_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_bf16                   vdst, src0
    v_cvt_f32_bf16_dpp               vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_bf16_sdwa              vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_bf8                    vdst, src0
    v_cvt_f32_bf8_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_bf8_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_f16                    vdst, src0
    v_cvt_f32_f16_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_f16_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_f64                    vdst, src0
    v_cvt_f32_f64_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_fp8                    vdst, src0
    v_cvt_f32_fp8_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_fp8_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_i32                    vdst, src0
    v_cvt_f32_i32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_i32_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_u32                    vdst, src0
    v_cvt_f32_u32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_u32_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_ubyte0                 vdst, src0
    v_cvt_f32_ubyte0_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_ubyte0_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_ubyte1                 vdst, src0
    v_cvt_f32_ubyte1_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_ubyte1_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_ubyte2                 vdst, src0
    v_cvt_f32_ubyte2_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_ubyte2_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f32_ubyte3                 vdst, src0
    v_cvt_f32_ubyte3_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f32_ubyte3_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_f64_f32                    vdst, src0
    v_cvt_f64_i32                    vdst, src0
    v_cvt_f64_i32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_f64_u32                    vdst, src0
    v_cvt_f64_u32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_flr_i32_f32                vdst, src0
    v_cvt_flr_i32_f32_dpp            vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_flr_i32_f32_sdwa           vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_i16_f16                    vdst, src0
    v_cvt_i16_f16_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_i16_f16_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_i32_f32                    vdst, src0
    v_cvt_i32_f32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_i32_f32_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_i32_f64                    vdst, src0
    v_cvt_i32_f64_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_norm_i16_f16               vdst, src0
    v_cvt_norm_i16_f16_dpp           vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_norm_i16_f16_sdwa          vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_norm_u16_f16               vdst, src0
    v_cvt_norm_u16_f16_dpp           vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_norm_u16_f16_sdwa          vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_off_f32_i4                 vdst, src0
    v_cvt_off_f32_i4_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_off_f32_i4_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_pk_f32_bf8                 vdst, src0
    v_cvt_pk_f32_bf8_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_pk_f32_bf8_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_pk_f32_fp8                 vdst, src0
    v_cvt_pk_f32_fp8_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_pk_f32_fp8_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_rpi_i32_f32                vdst, src0
    v_cvt_rpi_i32_f32_dpp            vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_rpi_i32_f32_sdwa           vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_u16_f16                    vdst, src0
    v_cvt_u16_f16_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_u16_f16_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_u32_f32                    vdst, src0
    v_cvt_u32_f32_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cvt_u32_f32_sdwa               vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_cvt_u32_f64                    vdst, src0
    v_cvt_u32_f64_dpp                vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_exp_f16                        vdst, src0
    v_exp_f16_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_exp_f16_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_exp_f32                        vdst, src0
    v_exp_f32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_exp_f32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_exp_legacy_f32                 vdst, src0
    v_exp_legacy_f32_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_exp_legacy_f32_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_ffbh_i32                       vdst, src0
    v_ffbh_i32_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ffbh_i32_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_ffbh_u32                       vdst, src0
    v_ffbh_u32_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ffbh_u32_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_ffbl_b32                       vdst, src0
    v_ffbl_b32_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ffbl_b32_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_floor_f16                      vdst, src0
    v_floor_f16_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_floor_f16_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_floor_f32                      vdst, src0
    v_floor_f32_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_floor_f32_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_floor_f64                      vdst, src0
    v_floor_f64_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_fract_f16                      vdst, src0
    v_fract_f16_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_fract_f16_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_fract_f32                      vdst, src0
    v_fract_f32_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_fract_f32_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_fract_f64                      vdst, src0
    v_fract_f64_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_frexp_exp_i16_f16              vdst, src0
    v_frexp_exp_i16_f16_dpp          vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_frexp_exp_i16_f16_sdwa         vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_frexp_exp_i32_f32              vdst, src0
    v_frexp_exp_i32_f32_dpp          vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_frexp_exp_i32_f32_sdwa         vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_frexp_exp_i32_f64              vdst, src0
    v_frexp_exp_i32_f64_dpp          vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_frexp_mant_f16                 vdst, src0
    v_frexp_mant_f16_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_frexp_mant_f16_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_frexp_mant_f32                 vdst, src0
    v_frexp_mant_f32_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_frexp_mant_f32_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_frexp_mant_f64                 vdst, src0
    v_frexp_mant_f64_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_log_f16                        vdst, src0
    v_log_f16_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_log_f16_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_log_f32                        vdst, src0
    v_log_f32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_log_f32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_log_legacy_f32                 vdst, src0
    v_log_legacy_f32_dpp             vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_log_legacy_f32_sdwa            vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_mov_b32                        vdst, src0
    v_mov_b32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mov_b32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_mov_b64                        vdst, src0
    v_mov_b64_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mov_b64_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_nop
    v_nop_dpp                                     bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_nop_sdwa                                    src0_sel src1_sel dst_sel dst_unused
    v_not_b32                        vdst, src0
    v_not_b32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_not_b32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_permlane16_swap_b32            vdst, src0
    v_permlane32_swap_b32            vdst, src0
    v_prng_b32                       vdst, src0
    v_prng_b32_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_prng_b32_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rcp_f16                        vdst, src0
    v_rcp_f16_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rcp_f16_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rcp_f32                        vdst, src0
    v_rcp_f32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rcp_f32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rcp_f64                        vdst, src0
    v_rcp_iflag_f32                  vdst, src0
    v_rcp_iflag_f32_dpp              vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rcp_iflag_f32_sdwa             vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_readfirstlane_b32              vdst, src0
    v_rndne_f16                      vdst, src0
    v_rndne_f16_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rndne_f16_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rndne_f32                      vdst, src0
    v_rndne_f32_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rndne_f32_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rndne_f64                      vdst, src0
    v_rsq_f16                        vdst, src0
    v_rsq_f16_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rsq_f16_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rsq_f32                        vdst, src0
    v_rsq_f32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_rsq_f32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_rsq_f64                        vdst, src0
    v_sat_pk_u8_i16                  vdst, src0
    v_sat_pk_u8_i16_dpp              vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sat_pk_u8_i16_sdwa             vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_screen_partition_4se_b32       vdst, src0
    v_screen_partition_4se_b32_dpp   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_screen_partition_4se_b32_sdwa  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_sin_f16                        vdst, src0
    v_sin_f16_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sin_f16_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_sin_f32                        vdst, src0
    v_sin_f32_dpp                    vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sin_f32_sdwa                   vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_sqrt_f16                       vdst, src0
    v_sqrt_f16_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sqrt_f16_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_sqrt_f32                       vdst, src0
    v_sqrt_f32_dpp                   vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sqrt_f32_sdwa                  vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_sqrt_f64                       vdst, src0
    v_swap_b32                       vdst, src0
    v_trunc_f16                      vdst, src0
    v_trunc_f16_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_trunc_f16_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_trunc_f32                      vdst, src0
    v_trunc_f32_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_trunc_f32_sdwa                 vdst, vsrc0  src0_sel src1_sel dst_sel dst_unused
    v_trunc_f64                      vdst, src0
    v_trunc_f64_dpp                  vdst, vsrc0  bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast

### VOP2

    INSTRUCTION            DST0  DST1  SRC0   SRC1     SRC2     MODIFIERS
    —————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_add_co_u32           vdst, vcc,  src0,  vsrc1
    v_add_co_u32_dpp       vdst, vcc,  vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_add_co_u32_sdwa      vdst, sdst, vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_add_f16              vdst,       src0,  vsrc1
    v_add_f16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_add_f16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_add_f32              vdst,       src0,  vsrc1
    v_add_f32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_add_f32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_add_u16              vdst,       src0,  vsrc1
    v_add_u16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_add_u16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_add_u32              vdst,       src0,  vsrc1
    v_add_u32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_add_u32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_addc_co_u32          vdst, vcc,  src0,  vsrc1,   vcc
    v_addc_co_u32_dpp      vdst, vcc,  vsrc0, vsrc1,   vcc      bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_addc_co_u32_sdwa     vdst, sdst, vsrc0, vsrc1,   vcc      src0_sel src1_sel dst_sel dst_unused
    v_and_b32              vdst,       src0,  vsrc1
    v_and_b32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_and_b32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_ashrrev_i16          vdst,       src0,  vsrc1
    v_ashrrev_i16_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ashrrev_i16_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_ashrrev_i32          vdst,       src0,  vsrc1
    v_ashrrev_i32_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ashrrev_i32_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_cndmask_b32          vdst,       src0,  vsrc1,   vcc
    v_cndmask_b32_dpp      vdst,       vsrc0, vsrc1,   vcc      bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_cndmask_b32_sdwa     vdst,       vsrc0, vsrc1,   vcc      src0_sel src1_sel dst_sel dst_unused
    v_dot2c_f32_bf16       vdst,       src0,  vsrc1
    v_dot2c_f32_bf16_dpp   vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_dot2c_f32_f16        vdst,       src0,  vsrc1
    v_dot2c_f32_f16_dpp    vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_dot2c_i32_i16        vdst,       src0,  vsrc1
    v_dot2c_i32_i16_dpp    vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_dot4c_i32_i8         vdst,       src0,  vsrc1
    v_dot4c_i32_i8_dpp     vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_dot8c_i32_i4         vdst,       src0,  vsrc1
    v_dot8c_i32_i4_dpp     vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_fmaak_f32            vdst,       src0,  vsrc1,   literal
    v_fmac_f32             vdst,       src0,  vsrc1
    v_fmac_f32_dpp         vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_fmac_f64             vdst,       src0,  vsrc1
    v_fmac_f64_dpp         vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_fmamk_f32            vdst,       src0,  literal, vsrc1
    v_ldexp_f16            vdst,       src0,  vsrc1
    v_ldexp_f16_dpp        vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_ldexp_f16_sdwa       vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_lshlrev_b16          vdst,       src0,  vsrc1
    v_lshlrev_b16_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_lshlrev_b16_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_lshlrev_b32          vdst,       src0,  vsrc1
    v_lshlrev_b32_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_lshlrev_b32_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_lshrrev_b16          vdst,       src0,  vsrc1
    v_lshrrev_b16_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_lshrrev_b16_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_lshrrev_b32          vdst,       src0,  vsrc1
    v_lshrrev_b32_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_lshrrev_b32_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mac_f16              vdst,       src0,  vsrc1
    v_mac_f16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_madak_f16            vdst,       src0,  vsrc1,   literal
    v_madmk_f16            vdst,       src0,  literal, vsrc1
    v_max_f16              vdst,       src0,  vsrc1
    v_max_f16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_max_f16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_max_f32              vdst,       src0,  vsrc1
    v_max_f32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_max_f32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_max_i16              vdst,       src0,  vsrc1
    v_max_i16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_max_i16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_max_i32              vdst,       src0,  vsrc1
    v_max_i32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_max_i32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_max_u16              vdst,       src0,  vsrc1
    v_max_u16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_max_u16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_max_u32              vdst,       src0,  vsrc1
    v_max_u32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_max_u32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_min_f16              vdst,       src0,  vsrc1
    v_min_f16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_min_f16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_min_f32              vdst,       src0,  vsrc1
    v_min_f32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_min_f32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_min_i16              vdst,       src0,  vsrc1
    v_min_i16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_min_i16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_min_i32              vdst,       src0,  vsrc1
    v_min_i32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_min_i32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_min_u16              vdst,       src0,  vsrc1
    v_min_u16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_min_u16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_min_u32              vdst,       src0,  vsrc1
    v_min_u32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_min_u32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_f16              vdst,       src0,  vsrc1
    v_mul_f16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_f16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_f32              vdst,       src0,  vsrc1
    v_mul_f32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_f32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_hi_i32_i24       vdst,       src0,  vsrc1
    v_mul_hi_i32_i24_dpp   vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_hi_i32_i24_sdwa  vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_hi_u32_u24       vdst,       src0,  vsrc1
    v_mul_hi_u32_u24_dpp   vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_hi_u32_u24_sdwa  vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_i32_i24          vdst,       src0,  vsrc1
    v_mul_i32_i24_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_i32_i24_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_lo_u16           vdst,       src0,  vsrc1
    v_mul_lo_u16_dpp       vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_lo_u16_sdwa      vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_mul_u32_u24          vdst,       src0,  vsrc1
    v_mul_u32_u24_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_mul_u32_u24_sdwa     vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_or_b32               vdst,       src0,  vsrc1
    v_or_b32_dpp           vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_or_b32_sdwa          vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_pk_fmac_f16          vdst,       src0,  vsrc1
    v_pk_fmac_f16_dpp      vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sub_co_u32           vdst, vcc,  src0,  vsrc1
    v_sub_co_u32_dpp       vdst, vcc,  vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sub_co_u32_sdwa      vdst, sdst, vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_sub_f16              vdst,       src0,  vsrc1
    v_sub_f16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sub_f16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_sub_f32              vdst,       src0,  vsrc1
    v_sub_f32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sub_f32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_sub_u16              vdst,       src0,  vsrc1
    v_sub_u16_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sub_u16_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_sub_u32              vdst,       src0,  vsrc1
    v_sub_u32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_sub_u32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_subb_co_u32          vdst, vcc,  src0,  vsrc1,   vcc
    v_subb_co_u32_dpp      vdst, vcc,  vsrc0, vsrc1,   vcc      bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subb_co_u32_sdwa     vdst, sdst, vsrc0, vsrc1,   vcc      src0_sel src1_sel dst_sel dst_unused
    v_subbrev_co_u32       vdst, vcc,  src0,  vsrc1,   vcc
    v_subbrev_co_u32_dpp   vdst, vcc,  vsrc0, vsrc1,   vcc      bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subbrev_co_u32_sdwa  vdst, sdst, vsrc0, vsrc1,   vcc      src0_sel src1_sel dst_sel dst_unused
    v_subrev_co_u32        vdst, vcc,  src0,  vsrc1
    v_subrev_co_u32_dpp    vdst, vcc,  vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subrev_co_u32_sdwa   vdst, sdst, vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_subrev_f16           vdst,       src0,  vsrc1
    v_subrev_f16_dpp       vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subrev_f16_sdwa      vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_subrev_f32           vdst,       src0,  vsrc1
    v_subrev_f32_dpp       vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subrev_f32_sdwa      vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_subrev_u16           vdst,       src0,  vsrc1
    v_subrev_u16_dpp       vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subrev_u16_sdwa      vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_subrev_u32           vdst,       src0,  vsrc1
    v_subrev_u32_dpp       vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_subrev_u32_sdwa      vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_xnor_b32             vdst,       src0,  vsrc1
    v_xnor_b32_dpp         vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_xnor_b32_sdwa        vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused
    v_xor_b32              vdst,       src0,  vsrc1
    v_xor_b32_dpp          vdst,       vsrc0, vsrc1             bank_mask row_mask bound_ctrl quad_perm row_shr row_shl row_ror row_bcast
    v_xor_b32_sdwa         vdst,       vsrc0, vsrc1             src0_sel src1_sel dst_sel dst_unused

### VOP3

    INSTRUCTION                     DST0      DST1      SRC0      SRC1      SRC2
    ——————————————————————————————————————————————————————————————————————————————————
    v_add3_u32                      vdst,               src0,     src1,     src2
    v_add_f64                       vdst,               src0,     src1
    v_add_i16                       vdst,               src0,     src1
    v_add_i32                       vdst,               src0,     src1
    v_add_lshl_u32                  vdst,               src0,     src1,     src2
    v_alignbit_b32                  vdst,               src0,     src1,     src2
    v_alignbyte_b32                 vdst,               src0,     src1,     src2
    v_and_or_b32                    vdst,               src0,     src1,     src2
    v_ashr_pk_i8_i32                vdst,               src0,     src1,     src2
    v_ashr_pk_u8_i32                vdst,               src0,     src1,     src2
    v_ashrrev_i64                   vdst,               src0,     src1
    v_bcnt_u32_b32                  vdst,               src0,     src1
    v_bfe_i32                       vdst,               src0,     src1,     src2
    v_bfe_u32                       vdst,               src0,     src1,     src2
    v_bfi_b32                       vdst,               src0,     src1,     src2
    v_bfm_b32                       vdst,               src0,     src1
    v_bitop3_b16                    vdst,               src0,     src1,     src2
    v_bitop3_b32                    vdst,               src0,     src1,     src2
    v_cubeid_f32                    vdst,               src0,     src1,     src2
    v_cubema_f32                    vdst,               src0,     src1,     src2
    v_cubesc_f32                    vdst,               src0,     src1,     src2
    v_cubetc_f32                    vdst,               src0,     src1,     src2
    v_cvt_pk_bf16_f32               vdst,               src0,     src1
    v_cvt_pk_bf8_f32                vdst,               src0,     src1
    v_cvt_pk_f16_f32                vdst,               src0,     src1
    v_cvt_pk_fp8_f32                vdst,               src0,     src1
    v_cvt_pk_i16_i32                vdst,               src0,     src1
    v_cvt_pk_u16_u32                vdst,               src0,     src1
    v_cvt_pk_u8_f32                 vdst,               src0,     src1,     src2
    v_cvt_pkaccum_u8_f32            vdst,               src0,     src1
    v_cvt_pknorm_i16_f16            vdst,               src0,     src1
    v_cvt_pknorm_i16_f32            vdst,               src0,     src1
    v_cvt_pknorm_u16_f16            vdst,               src0,     src1
    v_cvt_pknorm_u16_f32            vdst,               src0,     src1
    v_cvt_pkrtz_f16_f32             vdst,               src0,     src1
    v_cvt_scalef32_2xpk16_bf6_f32   vdst,               src0,     src1,     src2
    v_cvt_scalef32_2xpk16_fp6_f32   vdst,               src0,     src1,     src2
    v_cvt_scalef32_f16_bf8          vdst,               src0,     src1
    v_cvt_scalef32_f16_fp8          vdst,               src0,     src1
    v_cvt_scalef32_f32_bf8          vdst,               src0,     src1
    v_cvt_scalef32_f32_fp8          vdst,               src0,     src1
    v_cvt_scalef32_pk32_bf16_bf6    vdst,               src0,     src1
    v_cvt_scalef32_pk32_bf16_fp6    vdst,               src0,     src1
    v_cvt_scalef32_pk32_bf6_bf16    vdst,               src0,     src1
    v_cvt_scalef32_pk32_bf6_f16     vdst,               src0,     src1
    v_cvt_scalef32_pk32_f16_bf6     vdst,               src0,     src1
    v_cvt_scalef32_pk32_f16_fp6     vdst,               src0,     src1
    v_cvt_scalef32_pk32_f32_bf6     vdst,               src0,     src1
    v_cvt_scalef32_pk32_f32_fp6     vdst,               src0,     src1
    v_cvt_scalef32_pk32_fp6_bf16    vdst,               src0,     src1
    v_cvt_scalef32_pk32_fp6_f16     vdst,               src0,     src1
    v_cvt_scalef32_pk_bf16_bf8      vdst,               src0,     src1
    v_cvt_scalef32_pk_bf16_fp4      vdst,               src0,     src1
    v_cvt_scalef32_pk_bf16_fp8      vdst,               src0,     src1
    v_cvt_scalef32_pk_bf8_bf16      vdst,               src0,     src1
    v_cvt_scalef32_pk_bf8_f16       vdst,               src0,     src1
    v_cvt_scalef32_pk_bf8_f32       vdst,               src0,     src1,     src2
    v_cvt_scalef32_pk_f16_bf8       vdst,               src0,     src1
    v_cvt_scalef32_pk_f16_fp4       vdst,               src0,     src1
    v_cvt_scalef32_pk_f16_fp8       vdst,               src0,     src1
    v_cvt_scalef32_pk_f32_bf8       vdst,               src0,     src1
    v_cvt_scalef32_pk_f32_fp4       vdst,               src0,     src1
    v_cvt_scalef32_pk_f32_fp8       vdst,               src0,     src1
    v_cvt_scalef32_pk_fp4_bf16      vdst,               src0,     src1
    v_cvt_scalef32_pk_fp4_f16       vdst,               src0,     src1
    v_cvt_scalef32_pk_fp4_f32       vdst,               src0,     src1,     src2
    v_cvt_scalef32_pk_fp8_bf16      vdst,               src0,     src1
    v_cvt_scalef32_pk_fp8_f16       vdst,               src0,     src1
    v_cvt_scalef32_pk_fp8_f32       vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_bf8_bf16      vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_bf8_f16       vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_bf8_f32       vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_fp8_bf16      vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_fp8_f16       vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_fp8_f32       vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk32_bf6_bf16 vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk32_bf6_f16  vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk32_bf6_f32  vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk32_fp6_bf16 vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk32_fp6_f16  vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk32_fp6_f32  vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk_fp4_bf16   vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk_fp4_f16    vdst,               src0,     src1,     src2
    v_cvt_scalef32_sr_pk_fp4_f32    vdst,               src0,     src1,     src2
    v_cvt_sr_bf16_f32               vdst,               src0,     src1
    v_cvt_sr_bf8_f32                vdst,               src0,     src1
    v_cvt_sr_f16_f32                vdst,               src0,     src1
    v_cvt_sr_fp8_f32                vdst,               src0,     src1
    v_div_fixup_f16                 vdst,               src0,     src1,     src2
    v_div_fixup_f32                 vdst,               src0,     src1,     src2
    v_div_fixup_f64                 vdst,               src0,     src1,     src2
    v_div_fixup_legacy_f16          vdst,               src0,     src1,     src2
    v_div_fmas_f32                  vdst,               src0,     src1,     src2
    v_div_fmas_f64                  vdst,               src0,     src1,     src2
    v_div_scale_f32                 vdst,     sdst,     src0,     src1,     src2
    v_div_scale_f64                 vdst,     sdst,     src0,     src1,     src2
    v_fma_f16                       vdst,               src0,     src1,     src2
    v_fma_f32                       vdst,               src0,     src1,     src2
    v_fma_f64                       vdst,               src0,     src1,     src2
    v_fma_legacy_f16                vdst,               src0,     src1,     src2
    v_ldexp_f32                     vdst,               src0,     src1
    v_ldexp_f64                     vdst,               src0,     src1
    v_lerp_u8                       vdst,               src0,     src1,     src2
    v_lshl_add_u32                  vdst,               src0,     src1,     src2
    v_lshl_add_u64                  vdst,               src0,     src1,     src2
    v_lshl_or_b32                   vdst,               src0,     src1,     src2
    v_lshlrev_b64                   vdst,               src0,     src1
    v_lshrrev_b64                   vdst,               src0,     src1
    v_mad_f16                       vdst,               src0,     src1,     src2
    v_mad_i16                       vdst,               src0,     src1,     src2
    v_mad_i32_i16                   vdst,               src0,     src1,     src2
    v_mad_i32_i24                   vdst,               src0,     src1,     src2
    v_mad_i64_i32                   vdst,     sdst,     src0,     src1,     src2
    v_mad_legacy_f16                vdst,               src0,     src1,     src2
    v_mad_legacy_i16                vdst,               src0,     src1,     src2
    v_mad_legacy_u16                vdst,               src0,     src1,     src2
    v_mad_u16                       vdst,               src0,     src1,     src2
    v_mad_u32_u16                   vdst,               src0,     src1,     src2
    v_mad_u32_u24                   vdst,               src0,     src1,     src2
    v_mad_u64_u32                   vdst,     sdst,     src0,     src1,     src2
    v_max3_f16                      vdst,               src0,     src1,     src2
    v_max3_f32                      vdst,               src0,     src1,     src2
    v_max3_i16                      vdst,               src0,     src1,     src2
    v_max3_i32                      vdst,               src0,     src1,     src2
    v_max3_u16                      vdst,               src0,     src1,     src2
    v_max3_u32                      vdst,               src0,     src1,     src2
    v_max_f64                       vdst,               src0,     src1
    v_maximum3_f32                  vdst,               src0,     src1,     src2
    v_mbcnt_hi_u32_b32              vdst,               src0,     src1
    v_mbcnt_lo_u32_b32              vdst,               src0,     src1
    v_med3_f16                      vdst,               src0,     src1,     src2
    v_med3_f32                      vdst,               src0,     src1,     src2
    v_med3_i16                      vdst,               src0,     src1,     src2
    v_med3_i32                      vdst,               src0,     src1,     src2
    v_med3_u16                      vdst,               src0,     src1,     src2
    v_med3_u32                      vdst,               src0,     src1,     src2
    v_min3_f16                      vdst,               src0,     src1,     src2
    v_min3_f32                      vdst,               src0,     src1,     src2
    v_min3_i16                      vdst,               src0,     src1,     src2
    v_min3_i32                      vdst,               src0,     src1,     src2
    v_min3_u16                      vdst,               src0,     src1,     src2
    v_min3_u32                      vdst,               src0,     src1,     src2
    v_min_f64                       vdst,               src0,     src1
    v_minimum3_f32                  vdst,               src0,     src1,     src2
    v_mqsad_pk_u16_u8               vdst,               src0,     src1,     src2
    v_mqsad_u32_u8                  vdst,               src0,     src1,     src2
    v_msad_u8                       vdst,               src0,     src1,     src2
    v_mul_f64                       vdst,               src0,     src1
    v_mul_hi_i32                    vdst,               src0,     src1
    v_mul_hi_u32                    vdst,               src0,     src1
    v_mul_legacy_f32                vdst,               src0,     src1
    v_mul_lo_u32                    vdst,               src0,     src1
    v_or3_b32                       vdst,               src0,     src1,     src2
    v_pack_b32_f16                  vdst,               src0,     src1
    v_perm_b32                      vdst,               src0,     src1,     src2
    v_qsad_pk_u16_u8                vdst,               src0,     src1,     src2
    v_readlane_b32                  vdst,               src0,     src1
    v_sad_hi_u8                     vdst,               src0,     src1,     src2
    v_sad_u16                       vdst,               src0,     src1,     src2
    v_sad_u32                       vdst,               src0,     src1,     src2
    v_sad_u8                        vdst,               src0,     src1,     src2
    v_sub_i16                       vdst,               src0,     src1
    v_sub_i32                       vdst,               src0,     src1
    v_trig_preop_f64                vdst,               src0,     src1
    v_writelane_b32                 vdst,               src0,     src1
    v_xad_u32                       vdst,               src0,     src1,     src2

### VOP3P

    INSTRUCTION                        DST   SRC0  SRC1  SRC2      MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————
    v_accvgpr_read                     vdst, src0                  op_sel op_sel_hi neg_lo neg_hi clamp
    v_accvgpr_write                    vdst, src0                  op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot2_f32_bf16                    vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot2_f32_f16                     vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot2_i32_i16                     vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot2_u32_u16                     vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot4_i32_i8                      vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot4_u32_u8                      vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot8_i32_i4                      vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_dot8_u32_u4                      vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_mad_mix_f32                      vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_mad_mixhi_f16                    vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_mad_mixlo_f16                    vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_mfma_f32_16x16x128_f8f6f4        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x16_bf16           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x16_f16            vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x1_4b_f32          vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x32_bf16           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x32_bf8_bf8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x32_bf8_fp8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x32_f16            vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x32_fp8_bf8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x32_fp8_fp8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x4_4b_bf16         vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x4_4b_f16          vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_16x16x4_f32             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x16_bf16           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x16_bf8_bf8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x16_bf8_fp8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x16_f16            vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x16_fp8_bf8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x16_fp8_fp8        vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x1_2b_f32          vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x2_f32             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x4_2b_bf16         vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x4_2b_f16          vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x64_f8f6f4         vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x8_bf16            vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_32x32x8_f16             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_4x4x1_16b_f32           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_4x4x4_16b_bf16          vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f32_4x4x4_16b_f16           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f64_16x16x4_f64             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_f64_4x4x4_4b_f64            vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_16x16x32_i8             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_16x16x4_4b_i8           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_16x16x64_i8             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_32x32x16_i8             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_32x32x32_i8             vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_32x32x4_2b_i8           vdst, src0, src1, src2      blgp cbsz abid
    v_mfma_i32_4x4x4_16b_i8            vdst, src0, src1, src2      blgp cbsz abid
    v_pk_add_f16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_add_f32                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_add_i16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_add_u16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_ashrrev_i16                   vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_fma_f16                       vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_fma_f32                       vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_lshlrev_b16                   vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_lshrrev_b16                   vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mad_i16                       vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mad_u16                       vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_max_f16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_max_i16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_max_u16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_maximum3_f16                  vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_min_f16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_min_i16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_min_u16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_minimum3_f16                  vdst, src0, src1, src2      op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mov_b32                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mul_f16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mul_f32                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_mul_lo_u16                    vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_sub_i16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_pk_sub_u16                       vdst, src0, src1            op_sel op_sel_hi neg_lo neg_hi clamp
    v_smfmac_f32_16x16x128_bf8_bf8     vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x128_bf8_fp8     vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x128_fp8_bf8     vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x128_fp8_fp8     vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x32_bf16         vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x32_f16          vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x64_bf16         vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x64_bf8_bf8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x64_bf8_fp8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x64_f16          vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x64_fp8_bf8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_16x16x64_fp8_fp8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x16_bf16         vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x16_f16          vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x32_bf16         vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x32_bf8_bf8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x32_bf8_fp8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x32_f16          vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x32_fp8_bf8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x32_fp8_fp8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x64_bf8_bf8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x64_bf8_fp8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x64_fp8_bf8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_f32_32x32x64_fp8_fp8      vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_i32_16x16x128_i8          vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_i32_16x16x64_i8           vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_i32_32x32x32_i8           vdst, src0, src1, src2      blgp cbsz abid
    v_smfmac_i32_32x32x64_i8           vdst, src0, src1, src2      blgp cbsz abid

### VOP3PX2

    INSTRUCTION                        DST   SRC0  SRC1  SRC2  SRC3        SRC4        MODIFIERS
    ————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————————
    v_mfma_scale_f32_16x16x128_f8f6f4  vdst, src0, src1, src2, scale_src0, scale_src1  op_sel op_sel_hi neg_lo neg_hi blgp cbsz abid
    v_mfma_scale_f32_32x32x64_f8f6f4   vdst, src0, src1, src2, scale_src0, scale_src1  op_sel op_sel_hi neg_lo neg_hi blgp cbsz abid

### VOPC

    INSTRUCTION                    DST       SRC0      SRC1        MODIFIERS
    ———————————————————————————————————————————————————————————————————————————————————————————————————
    v_cmp_class_f16                vcc,      src0,     vsrc1
    v_cmp_class_f16_sdwa           sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_class_f32                vcc,      src0,     vsrc1
    v_cmp_class_f32_sdwa           sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_class_f64                vcc,      src0,     vsrc1
    v_cmp_eq_f16                   vcc,      src0,     vsrc1
    v_cmp_eq_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_eq_f32                   vcc,      src0,     vsrc1
    v_cmp_eq_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_eq_f64                   vcc,      src0,     vsrc1
    v_cmp_eq_i16                   vcc,      src0,     vsrc1
    v_cmp_eq_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_eq_i32                   vcc,      src0,     vsrc1
    v_cmp_eq_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_eq_i64                   vcc,      src0,     vsrc1
    v_cmp_eq_u16                   vcc,      src0,     vsrc1
    v_cmp_eq_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_eq_u32                   vcc,      src0,     vsrc1
    v_cmp_eq_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_eq_u64                   vcc,      src0,     vsrc1
    v_cmp_f_f16                    vcc,      src0,     vsrc1
    v_cmp_f_f16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_f_f32                    vcc,      src0,     vsrc1
    v_cmp_f_f32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_f_f64                    vcc,      src0,     vsrc1
    v_cmp_f_i16                    vcc,      src0,     vsrc1
    v_cmp_f_i16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_f_i32                    vcc,      src0,     vsrc1
    v_cmp_f_i32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_f_i64                    vcc,      src0,     vsrc1
    v_cmp_f_u16                    vcc,      src0,     vsrc1
    v_cmp_f_u16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_f_u32                    vcc,      src0,     vsrc1
    v_cmp_f_u32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_f_u64                    vcc,      src0,     vsrc1
    v_cmp_ge_f16                   vcc,      src0,     vsrc1
    v_cmp_ge_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ge_f32                   vcc,      src0,     vsrc1
    v_cmp_ge_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ge_f64                   vcc,      src0,     vsrc1
    v_cmp_ge_i16                   vcc,      src0,     vsrc1
    v_cmp_ge_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ge_i32                   vcc,      src0,     vsrc1
    v_cmp_ge_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ge_i64                   vcc,      src0,     vsrc1
    v_cmp_ge_u16                   vcc,      src0,     vsrc1
    v_cmp_ge_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ge_u32                   vcc,      src0,     vsrc1
    v_cmp_ge_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ge_u64                   vcc,      src0,     vsrc1
    v_cmp_gt_f16                   vcc,      src0,     vsrc1
    v_cmp_gt_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_gt_f32                   vcc,      src0,     vsrc1
    v_cmp_gt_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_gt_f64                   vcc,      src0,     vsrc1
    v_cmp_gt_i16                   vcc,      src0,     vsrc1
    v_cmp_gt_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_gt_i32                   vcc,      src0,     vsrc1
    v_cmp_gt_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_gt_i64                   vcc,      src0,     vsrc1
    v_cmp_gt_u16                   vcc,      src0,     vsrc1
    v_cmp_gt_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_gt_u32                   vcc,      src0,     vsrc1
    v_cmp_gt_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_gt_u64                   vcc,      src0,     vsrc1
    v_cmp_le_f16                   vcc,      src0,     vsrc1
    v_cmp_le_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_le_f32                   vcc,      src0,     vsrc1
    v_cmp_le_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_le_f64                   vcc,      src0,     vsrc1
    v_cmp_le_i16                   vcc,      src0,     vsrc1
    v_cmp_le_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_le_i32                   vcc,      src0,     vsrc1
    v_cmp_le_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_le_i64                   vcc,      src0,     vsrc1
    v_cmp_le_u16                   vcc,      src0,     vsrc1
    v_cmp_le_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_le_u32                   vcc,      src0,     vsrc1
    v_cmp_le_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_le_u64                   vcc,      src0,     vsrc1
    v_cmp_lg_f16                   vcc,      src0,     vsrc1
    v_cmp_lg_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lg_f32                   vcc,      src0,     vsrc1
    v_cmp_lg_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lg_f64                   vcc,      src0,     vsrc1
    v_cmp_lt_f16                   vcc,      src0,     vsrc1
    v_cmp_lt_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lt_f32                   vcc,      src0,     vsrc1
    v_cmp_lt_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lt_f64                   vcc,      src0,     vsrc1
    v_cmp_lt_i16                   vcc,      src0,     vsrc1
    v_cmp_lt_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lt_i32                   vcc,      src0,     vsrc1
    v_cmp_lt_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lt_i64                   vcc,      src0,     vsrc1
    v_cmp_lt_u16                   vcc,      src0,     vsrc1
    v_cmp_lt_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lt_u32                   vcc,      src0,     vsrc1
    v_cmp_lt_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_lt_u64                   vcc,      src0,     vsrc1
    v_cmp_ne_i16                   vcc,      src0,     vsrc1
    v_cmp_ne_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ne_i32                   vcc,      src0,     vsrc1
    v_cmp_ne_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ne_i64                   vcc,      src0,     vsrc1
    v_cmp_ne_u16                   vcc,      src0,     vsrc1
    v_cmp_ne_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ne_u32                   vcc,      src0,     vsrc1
    v_cmp_ne_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ne_u64                   vcc,      src0,     vsrc1
    v_cmp_neq_f16                  vcc,      src0,     vsrc1
    v_cmp_neq_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_neq_f32                  vcc,      src0,     vsrc1
    v_cmp_neq_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_neq_f64                  vcc,      src0,     vsrc1
    v_cmp_nge_f16                  vcc,      src0,     vsrc1
    v_cmp_nge_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nge_f32                  vcc,      src0,     vsrc1
    v_cmp_nge_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nge_f64                  vcc,      src0,     vsrc1
    v_cmp_ngt_f16                  vcc,      src0,     vsrc1
    v_cmp_ngt_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ngt_f32                  vcc,      src0,     vsrc1
    v_cmp_ngt_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_ngt_f64                  vcc,      src0,     vsrc1
    v_cmp_nle_f16                  vcc,      src0,     vsrc1
    v_cmp_nle_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nle_f32                  vcc,      src0,     vsrc1
    v_cmp_nle_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nle_f64                  vcc,      src0,     vsrc1
    v_cmp_nlg_f16                  vcc,      src0,     vsrc1
    v_cmp_nlg_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nlg_f32                  vcc,      src0,     vsrc1
    v_cmp_nlg_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nlg_f64                  vcc,      src0,     vsrc1
    v_cmp_nlt_f16                  vcc,      src0,     vsrc1
    v_cmp_nlt_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nlt_f32                  vcc,      src0,     vsrc1
    v_cmp_nlt_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_nlt_f64                  vcc,      src0,     vsrc1
    v_cmp_o_f16                    vcc,      src0,     vsrc1
    v_cmp_o_f16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_o_f32                    vcc,      src0,     vsrc1
    v_cmp_o_f32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_o_f64                    vcc,      src0,     vsrc1
    v_cmp_t_i16                    vcc,      src0,     vsrc1
    v_cmp_t_i16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_t_i32                    vcc,      src0,     vsrc1
    v_cmp_t_i32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_t_i64                    vcc,      src0,     vsrc1
    v_cmp_t_u16                    vcc,      src0,     vsrc1
    v_cmp_t_u16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_t_u32                    vcc,      src0,     vsrc1
    v_cmp_t_u32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_t_u64                    vcc,      src0,     vsrc1
    v_cmp_tru_f16                  vcc,      src0,     vsrc1
    v_cmp_tru_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_tru_f32                  vcc,      src0,     vsrc1
    v_cmp_tru_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_tru_f64                  vcc,      src0,     vsrc1
    v_cmp_u_f16                    vcc,      src0,     vsrc1
    v_cmp_u_f16_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_u_f32                    vcc,      src0,     vsrc1
    v_cmp_u_f32_sdwa               sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmp_u_f64                    vcc,      src0,     vsrc1
    v_cmpx_class_f16               vcc,      src0,     vsrc1
    v_cmpx_class_f16_sdwa          sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_class_f32               vcc,      src0,     vsrc1
    v_cmpx_class_f32_sdwa          sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_class_f64               vcc,      src0,     vsrc1
    v_cmpx_eq_f16                  vcc,      src0,     vsrc1
    v_cmpx_eq_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_eq_f32                  vcc,      src0,     vsrc1
    v_cmpx_eq_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_eq_f64                  vcc,      src0,     vsrc1
    v_cmpx_eq_i16                  vcc,      src0,     vsrc1
    v_cmpx_eq_i16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_eq_i32                  vcc,      src0,     vsrc1
    v_cmpx_eq_i32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_eq_i64                  vcc,      src0,     vsrc1
    v_cmpx_eq_u16                  vcc,      src0,     vsrc1
    v_cmpx_eq_u16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_eq_u32                  vcc,      src0,     vsrc1
    v_cmpx_eq_u32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_eq_u64                  vcc,      src0,     vsrc1
    v_cmpx_f_f16                   vcc,      src0,     vsrc1
    v_cmpx_f_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_f_f32                   vcc,      src0,     vsrc1
    v_cmpx_f_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_f_f64                   vcc,      src0,     vsrc1
    v_cmpx_f_i16                   vcc,      src0,     vsrc1
    v_cmpx_f_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_f_i32                   vcc,      src0,     vsrc1
    v_cmpx_f_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_f_i64                   vcc,      src0,     vsrc1
    v_cmpx_f_u16                   vcc,      src0,     vsrc1
    v_cmpx_f_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_f_u32                   vcc,      src0,     vsrc1
    v_cmpx_f_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_f_u64                   vcc,      src0,     vsrc1
    v_cmpx_ge_f16                  vcc,      src0,     vsrc1
    v_cmpx_ge_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ge_f32                  vcc,      src0,     vsrc1
    v_cmpx_ge_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ge_f64                  vcc,      src0,     vsrc1
    v_cmpx_ge_i16                  vcc,      src0,     vsrc1
    v_cmpx_ge_i16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ge_i32                  vcc,      src0,     vsrc1
    v_cmpx_ge_i32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ge_i64                  vcc,      src0,     vsrc1
    v_cmpx_ge_u16                  vcc,      src0,     vsrc1
    v_cmpx_ge_u16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ge_u32                  vcc,      src0,     vsrc1
    v_cmpx_ge_u32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ge_u64                  vcc,      src0,     vsrc1
    v_cmpx_gt_f16                  vcc,      src0,     vsrc1
    v_cmpx_gt_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_gt_f32                  vcc,      src0,     vsrc1
    v_cmpx_gt_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_gt_f64                  vcc,      src0,     vsrc1
    v_cmpx_gt_i16                  vcc,      src0,     vsrc1
    v_cmpx_gt_i16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_gt_i32                  vcc,      src0,     vsrc1
    v_cmpx_gt_i32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_gt_i64                  vcc,      src0,     vsrc1
    v_cmpx_gt_u16                  vcc,      src0,     vsrc1
    v_cmpx_gt_u16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_gt_u32                  vcc,      src0,     vsrc1
    v_cmpx_gt_u32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_gt_u64                  vcc,      src0,     vsrc1
    v_cmpx_le_f16                  vcc,      src0,     vsrc1
    v_cmpx_le_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_le_f32                  vcc,      src0,     vsrc1
    v_cmpx_le_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_le_f64                  vcc,      src0,     vsrc1
    v_cmpx_le_i16                  vcc,      src0,     vsrc1
    v_cmpx_le_i16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_le_i32                  vcc,      src0,     vsrc1
    v_cmpx_le_i32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_le_i64                  vcc,      src0,     vsrc1
    v_cmpx_le_u16                  vcc,      src0,     vsrc1
    v_cmpx_le_u16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_le_u32                  vcc,      src0,     vsrc1
    v_cmpx_le_u32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_le_u64                  vcc,      src0,     vsrc1
    v_cmpx_lg_f16                  vcc,      src0,     vsrc1
    v_cmpx_lg_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lg_f32                  vcc,      src0,     vsrc1
    v_cmpx_lg_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lg_f64                  vcc,      src0,     vsrc1
    v_cmpx_lt_f16                  vcc,      src0,     vsrc1
    v_cmpx_lt_f16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lt_f32                  vcc,      src0,     vsrc1
    v_cmpx_lt_f32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lt_f64                  vcc,      src0,     vsrc1
    v_cmpx_lt_i16                  vcc,      src0,     vsrc1
    v_cmpx_lt_i16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lt_i32                  vcc,      src0,     vsrc1
    v_cmpx_lt_i32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lt_i64                  vcc,      src0,     vsrc1
    v_cmpx_lt_u16                  vcc,      src0,     vsrc1
    v_cmpx_lt_u16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lt_u32                  vcc,      src0,     vsrc1
    v_cmpx_lt_u32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_lt_u64                  vcc,      src0,     vsrc1
    v_cmpx_ne_i16                  vcc,      src0,     vsrc1
    v_cmpx_ne_i16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ne_i32                  vcc,      src0,     vsrc1
    v_cmpx_ne_i32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ne_i64                  vcc,      src0,     vsrc1
    v_cmpx_ne_u16                  vcc,      src0,     vsrc1
    v_cmpx_ne_u16_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ne_u32                  vcc,      src0,     vsrc1
    v_cmpx_ne_u32_sdwa             sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ne_u64                  vcc,      src0,     vsrc1
    v_cmpx_neq_f16                 vcc,      src0,     vsrc1
    v_cmpx_neq_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_neq_f32                 vcc,      src0,     vsrc1
    v_cmpx_neq_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_neq_f64                 vcc,      src0,     vsrc1
    v_cmpx_nge_f16                 vcc,      src0,     vsrc1
    v_cmpx_nge_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nge_f32                 vcc,      src0,     vsrc1
    v_cmpx_nge_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nge_f64                 vcc,      src0,     vsrc1
    v_cmpx_ngt_f16                 vcc,      src0,     vsrc1
    v_cmpx_ngt_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ngt_f32                 vcc,      src0,     vsrc1
    v_cmpx_ngt_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_ngt_f64                 vcc,      src0,     vsrc1
    v_cmpx_nle_f16                 vcc,      src0,     vsrc1
    v_cmpx_nle_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nle_f32                 vcc,      src0,     vsrc1
    v_cmpx_nle_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nle_f64                 vcc,      src0,     vsrc1
    v_cmpx_nlg_f16                 vcc,      src0,     vsrc1
    v_cmpx_nlg_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nlg_f32                 vcc,      src0,     vsrc1
    v_cmpx_nlg_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nlg_f64                 vcc,      src0,     vsrc1
    v_cmpx_nlt_f16                 vcc,      src0,     vsrc1
    v_cmpx_nlt_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nlt_f32                 vcc,      src0,     vsrc1
    v_cmpx_nlt_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_nlt_f64                 vcc,      src0,     vsrc1
    v_cmpx_o_f16                   vcc,      src0,     vsrc1
    v_cmpx_o_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_o_f32                   vcc,      src0,     vsrc1
    v_cmpx_o_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_o_f64                   vcc,      src0,     vsrc1
    v_cmpx_t_i16                   vcc,      src0,     vsrc1
    v_cmpx_t_i16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_t_i32                   vcc,      src0,     vsrc1
    v_cmpx_t_i32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_t_i64                   vcc,      src0,     vsrc1
    v_cmpx_t_u16                   vcc,      src0,     vsrc1
    v_cmpx_t_u16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_t_u32                   vcc,      src0,     vsrc1
    v_cmpx_t_u32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_t_u64                   vcc,      src0,     vsrc1
    v_cmpx_tru_f16                 vcc,      src0,     vsrc1
    v_cmpx_tru_f16_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_tru_f32                 vcc,      src0,     vsrc1
    v_cmpx_tru_f32_sdwa            sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_tru_f64                 vcc,      src0,     vsrc1
    v_cmpx_u_f16                   vcc,      src0,     vsrc1
    v_cmpx_u_f16_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_u_f32                   vcc,      src0,     vsrc1
    v_cmpx_u_f32_sdwa              sdst,     vsrc0,    vsrc1       src0_sel src1_sel dst_sel dst_unused
    v_cmpx_u_f64                   vcc,      src0,     vsrc1