User Guides — LLVM 23.1.0 documentation

# User Guides

NOTE: If you are a user who is only interested in using an LLVM-based compiler, you should look into Clang instead. The documentation here is intended for users who have a need to work with the intermediate LLVM representation.

## Clang

- How To Build On ARM

  Notes on building and testing LLVM/Clang on ARM.

- How To Build Clang and LLVM with Profile-Guided Optimizations

  Notes on building LLVM/Clang with PGO.

- How to cross-compile Clang/LLVM using Clang/LLVM

  Notes on cross-building and testing LLVM/Clang.

- How to build the C, C++, ObjC, and ObjC++ front end

  Instructions for building the clang front-end from source.

- LLVM Code Coverage Mapping Format

  This describes the format and encoding used for LLVM’s code coverage mapping.

- Control Flow Verification Tool Design Document

  A description of the verification tool for Control Flow Integrity.

## LLVM Builds and Distributions

- Building a Distribution of LLVM

  A best-practices guide for using LLVM’s CMake build system to package and distribute LLVM-based tools.

- Building LLVM with CMake

  An addendum to the main Getting Started guide for those using the CMake build system.

- A guide to Dockerfiles for building LLVM

  A reference for using Dockerfiles provided with LLVM.

- Support Library

  This document describes the LLVM Support Library (`lib/Support`) and how to keep LLVM source code portable.

- Advanced Build Configurations

  This document describes more advanced build configurations.

## Optimizations

- Writing an LLVM Pass

  Information on how to write LLVM transformations under the new pass manager.

- Writing an LLVM Pass (legacy PM version)

  Information on how to write LLVM transformations and analyses under the legacy pass manager.

- LLVM’s Analysis and Transform Passes

  A list of optimizations and analyses implemented in LLVM.

- Stack Safety Analysis

  This document describes the design of the stack safety analysis of local variables.

- MergeFunctions pass, how it works

  Describes functions merging optimization.

- LLVM Alias Analysis Infrastructure

  Information on how to write a new alias analysis implementation or how to use existing analyses.

- MemorySSA

  Information about the MemorySSA utility in LLVM, as well as how to use it.

- MemProf: Memory Profiling for LLVM

  User guide and internals of MemProf, profile guided optimizations for memory.

- LLVM Loop Terminology (and Canonical Forms)

  A document describing Loops and associated terms as used in LLVM.

- LLVM Cycle Terminology

  A document describing cycles as a generalization of loops.

- Auto-Vectorization in LLVM

  This document describes the current status of vectorization in LLVM.

- LLVM Link Time Optimization: Design and Implementation

  This document describes the interface between LLVM intermodular optimizer and the linker and its design

- DTLTO

  This document describes the DTLTO implementation, which allows for distributing ThinLTO backend compilations without requiring support from the build system.

- The LLVM gold plugin

  How to build your programs with link-time optimization on Linux.

- Remarks

  A reference on the implementation of remarks in LLVM.

- Source Level Debugging with LLVM

  This document describes the design and philosophy behind the LLVM source-level debugger.

- How to Update Debug Info

  This document specifies how to correctly update debug info in various kinds of code transformations.

- Instruction referencing for debug info

  This document explains how LLVM uses value tracking, or instruction referencing, to determine variable locations for debug info in the final stages of compilation.

- Debug info migration: From intrinsics to records

  This is a migration guide describing how to move from debug info using intrinsics such as dbg.value to using the non-instruction DbgRecord object.

- Key Instructions debug info in LLVM and Clang

  This document explains how the debug info feature Key Instructions is implemented in LLVM.

- Instrumentation Profile Format

  This document explains two binary formats of instrumentation-based profiles.

- InstCombine contributor guide

  This document specifies guidelines for contributions for InstCombine and related passes.

- The LLVM Instrumentor Pass

  A comprehensive guide to the highly configurable Instrumentor pass for custom program instrumentation, including the interactive configuration wizard.

## Code Generation

- Writing an LLVM Backend

  Information on how to write LLVM backends for machine targets.

- The LLVM Target-Independent Code Generator

  The design and implementation of the LLVM code generator. Useful if you are working on retargetting LLVM to a new architecture, designing a new codegen pass, or enhancing existing components.

- TableGen

  Describes the TableGen tool, which is used heavily by the LLVM code generator.

### GlobalISel

- MIRPatterns

  Describes the design of MIR Patterns and how to use them.

### JIT

- MCJIT Design and Implementation

  Describes the inner workings of MCJIT execution engine.

- ORC Design and Implementation

  Describes the design and implementation of the ORC APIs, including some usage examples, and a guide for users transitioning from ORCv1 to ORCv2.

- JITLink and ORC’s ObjectLinkingLayer

  Describes the design and APIs for the JITLink library, ORC’s new JIT linker.

- Debugging JIT-ed Code

  How to debug JITed code with GDB.

## Additional Topics

- CommandLine 2.0 Library Manual

  Provides information on using the command line parsing library.

- Extending LLVM: Adding instructions, intrinsics, types, etc.

  Look here to see how to add instructions and intrinsics to LLVM.

- How To Add A Constrained Floating-Point Intrinsic

  Gives the steps necessary when adding a new constrained math intrinsic to LLVM.

- How to build Windows Itanium applications.

  Notes on assembling a Windows Itanium environment.

- How to Cross Compile Compiler-rt Builtins For Arm

  Notes on cross-building and testing the compiler-rt builtins for Arm.

- Using ARM NEON instructions in big-endian mode

  LLVM’s support for generating NEON instructions on big endian ARM targets is somewhat nonintuitive. This document explains the implementation and rationale.

- Support for AArch64 Scalable Matrix Extension in LLVM

  LLVM’s support for AArch64 SME ACLE and ABI.

- Compiling CUDA with clang

  LLVM support for CUDA.

- User Guide for NVPTX Back-end

  This document describes using the NVPTX backend to compile GPU kernels.

- User Guide for AMDGPU Backend

  This document describes using the AMDGPU backend to compile GPU kernels.

- AMDGPU Asynchronous Operations

  Asynchronous operations and the asyncmark mechanism for tracking their completion on AMD GPUs.

- AMDGPU DMA Operations

  DMA operations that transfer data between global memory and LDS on AMD GPUs.

- AMDGPU Memory Model

  This document describes AMDGPU Memory Model which overrides the LLVM memory model when a program is compiled for the AMDGPU target.

- DWARF Extensions For Heterogeneous Debugging

  This document describes DWARF extensions to support heterogeneous debugging for targets such as the AMDGPU backend.

- Allow Location Descriptions on the DWARF Expression Stack

  This document describes a DWARF extension to allow location descriptions on the DWARF expression stack. It is part of DWARF Extensions For Heterogeneous Debugging.

- AMDGPU Execution Synchronization

  This document describes how execution of threads can be synchronized on AMD GPUs.

- User Guide for SPIR-V Target

  This document describes using the SPIR-V target to compile GPU kernels.

- User Guide for the DirectX Target

  This document describes using the DirectX target to compile GPU code for the DirectX runtime.

- User Guide for RISC-V Target

  This document describes using the RISC-V target.

- RISC-V Vector Extension

  This document describes how the RISC-V Vector extension can be expressed in LLVM IR and how code is generated for it in the backend.

- Scheduling Information for RISC-V VCIX Instructions

  This document shows how the scheduling information for RISC-V’s `XSfvcp` extension – SiFive Vector Coprocessor Interface (VCIX) – works and how to customize them.

- Sandbox IR

  This document describes the design and usage of Sandbox IR, a transactional layer over LLVM IR.

- Telemetry framework in LLVM

  This document describes the Telemetry framework in LLVM.

- LFI

  This document describes the Lightweight Fault Isolation (LFI) target in LLVM.